Summary

This chapter introduced the basic workflow and tools for generating bare-metal RISC-V assembly from high-level languages.

Assembly is a precise description that maps closely to the processor’s structure and instruction semantics. The goal here is not to require you to handwrite complex assembly, but to help you read the assembly that appears in later labs and understand its relationship to instruction formats, datapaths, and control signals.

In the next chapters, these tool-generated assembly programs will be used as test cases to run on the CPUs you design and implement.