Lab Index
This index collects all sections titled Experiment, in the order they appear.
Part 1 - Digital Logic
Section titled “Part 1 - Digital Logic”Chapter 1 — Getting Started
Section titled “Chapter 1 — Getting Started”Chapter 2 — Combinational Logic Design
Section titled “Chapter 2 — Combinational Logic Design”- Experiment: Multiplexer and Decoder (Gate-Level Implementation)
- Experiment: Hierarchical adder design
- Experiment: Adder/Subtractor
- Experiment: Arithmetic Logic Unit (ALU)
Chapter 3 — Sequential Logic Design
Section titled “Chapter 3 — Sequential Logic Design”- Experiment: Level-triggered vs edge-triggered behavior
- Experiment: 4-bit synchronous parallel register
- Experiment: 4×8 multi-port register file
- Experiment: Sequence detector (pattern 101)
- Experiment: 3-digit decimal counter (000 → 999)
Part 2 - Processor Architecture
Section titled “Part 2 - Processor Architecture”Chapter 5 — Single-Cycle CPU: Design & Implementation
Section titled “Chapter 5 — Single-Cycle CPU: Design & Implementation”- Experiment: Build the datapath for
ADDI - Experiment: Add the datapath for
LW - Experiment: Datapath analysis for R-type, S-type, and B-type instructions
- Experiment: Single-cycle control unit
- Experiment: Single-cycle CPU integration and validation
Chapter 6 — Pipeline Analysis (Ripes)
Section titled “Chapter 6 — Pipeline Analysis (Ripes)”- Experiment: Basic execution in a five-stage pipeline
- Experiment: Data hazard — stalls vs forwarding
- Experiment: Control hazard — branch decision and flush
Part 3 - Memory Systems
Section titled “Part 3 - Memory Systems”Chapter 7 — Memory Expansion & Error Checking
Section titled “Chapter 7 — Memory Expansion & Error Checking”- Experiment: Parallel organization of memory chips
- Experiment: Address mapping and chip select
- Experiment: Hamming code detection and correction
Chapter 8 — Cache
Section titled “Chapter 8 — Cache”- Experiment: LRU vs Random
- Experiment: Cache mapping behavior
- Experiment: Dirty bit and write-back observation